1. Field of the Invention
The present invention relates to a production method for manufacturing a plurality of chip-size packages, each of which has substantially the same size or extent as a semiconductor device included therein and sealed with a suitable resin material.
2. Description of the Related Art
As well known, a chip-size package (CSP) has been developed so as to meet the demands of higher performance, smaller and lighter size, and higher speed for a piece of electronic equipment. Namely, inherently, there is a demand for more miniaturization, higher performance, and lower production cost of the chip-size package per se.
In a representative conventional production method for manufacturing chip-size packages, for example, a silicon wafer is prepared, and a surface of the silicon wafer is sectioned into a plurality of semiconductor chip areas by forming grid-like fine grooves (i.e. scribe lines) in the silicon wafer. Then, the silicon wafer is processed by various well-known methods such that each of the semiconductor chip areas is produced as a semiconductor device. Subsequently, a plurality of electrode pads are formed and arranged on each of the semiconductor chip areas, and respective metal bumps are bonded on the electrode pads. Namely, each of the semiconductor devices is formed as a flip-chip (FC) type semiconductor device. Thereafter, the silicon wafer is subjected to a dicing process in which the silicon wafer is cut along the grid-like grooves defining the FC type semiconductor devices, so that the FC type semiconductor devices are separated from each other.
On the other hand, in the production of the chip-size packages, a plurality of wiring-boards, each of which is usually called a package board or interposer, are prepared, with each of the interposers having substantially the same size or extent as an FC type semiconductor device. Also, each of the interposers includes a plurality of upper electrode pads formed on an upper surface thereof, a plurality of lower electrode pads formed on a lower surface thereof, a plurality of solder balls bonded on the lower electrode pads formed on the bottom surface of the interposer, and an internal wiring-arrangement provided between the upper and lower surfaces of the interposer to establish electrical connections between the upper and lower electrode pads.
After the aforesaid dicing process, each of the separated FC type semiconductor devices is flipped over and put in place on the upper surface of an interposer such that the respective metal bumps of the FC type semiconductor device are in electrical contact with the upper electrode pads formed on the upper surface of the interposer. Then, the metal bumps of the FC type semiconductor device are securely bonded on the upper electrode pads of the interposer by using either an ultrasonic-pressure bonding method or a heat-pressure bonding method. Subsequently, a resin-underfilling process is carried out such that a space between the FC type semiconductor device and the interposer is filled with a suitable resin material, to thereby seal the arrangement of metal bumps, resulting in the production of the chip-size package.
The above-mentioned conventional production method for manufacturing the chip-size packages is very inefficient in that the separated FC type semiconductor devices must be individually combined with the interposers, and then must be individually sealed with the suitable resin material.
In order to efficiently manufacture a large quantity of chip-size packages, it has been proposed that the chip-size packages be produced in a lump on semiconductor chip areas defined on a silicon wafer, without using any interposers, and that the silicon wafer then be cut so that the chip-size packages are separated from each other, as disclosed in, for example, JP-A-09-064049, JP-A-11-135549, and JP-A-2001-203297.
In particular, similar to the above-mentioned case, a plurality of semiconductor devices are produced on a silicon wafer, a plurality of electrode pads are formed on each of the semiconductor chip areas, and respective metal bumps are bonded on the electrode pads. Then, the surface of the silicon wafer, on which both the electrode pads and the metal bumps are provided, is coated with a suitable uncured resin material to thereby produce a resin-sealing layer, as disclosed in JP-A-09-064049. Otherwise, an adhesive resin-sealing sheet containing an uncured thermosetting resin is applied to and pressed against the surface of the silicon wafer such that the electrode pads the metal bumps are penetrated into the adhesive resin-sealing sheet, to thereby produce a resin-sealing layer, as disclosed in JP-A-2001-203297.
In either case, after the resin-sealing layer is completely cured, it is subjected to a polishing process. Namely, the surface of the resin-sealing layer is polished so that top faces of the metal bumps are exposed to the outside, and a metal layer is formed on the polished surface of the resin-sealing layer.
Subsequently, the metal layer is patterned by using a photolithography process and an etching process so that a plurality of conducting paths are formed on the surface of the resin-sealing layer, with each of the conducting paths being in electrical contact with an exposed top face of a corresponding metal bump. Thereafter, a plurality of solder balls are bonded on the conducting paths, whereby a plurality of chip-size package are produced on the silicon wafer. Then, the silicon wafer is subjected to a dicing process, so that the chip-size packages are cut and separated from each other, resulting in the production of the plurality of chip-size packages in a lump.
According to this second conventional production method, it is possible to more efficiently manufacture the large quantity of chip-size packages in comparison with the aforesaid first conventional production method in that the plurality of chip-size packages are produced in a lump on the silicon wafer. Nevertheless, there is a room for further improvement of the second conventional production method.
In particular, as stated above, the second conventional production method involves the polishing process, but this polishing process is relatively troublesome because the residue produced in the polishing process must be rinsed off from the polished silicon wafer.